1. Field of the Invention
Embodiments of the present invention relate generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to improved semiconductor devices and improved fabrication techniques for semiconductor devices.
2. Description of the Related Art
As electronics continue toward greater miniaturization and faster processing speeds, various techniques have been developed for more compact packaging and increased transmission speeds in semiconductor chips. For example, one trend has been the stacking of circuit components in multiple layers on a chip. This allows more components to be fabricated in a given area and also reduces the lengths of the vertical interconnects, the conductive lines that electrically couple the circuit components on the chip. Decreasing the length of these electrical connections reduces RC delay and wire inductance, thereby increasing the signal transmission speed. Another trend in semiconductor fabrication has been the use of narrower interconnects. The use of narrower interconnects reduces the amount of chip real-estate that is used by electrical connections, and permits more circuit components to be fabricated within a given area.
One drawback of narrower vertical interconnects, however, is that the smaller cross-sectional area of the conductive material in the interconnect may increase the electrical resistance of the interconnect, resulting in increased heat and a greater likelihood of device failure. Furthermore, a typical interconnect usually includes resistive layers, such as a barrier layer used to prevent electrical and chemical interactions between the conductive interconnect and the surrounding dielectric and a seed layer used to promote the growth of the conductive metal within the interconnect. These resistive layers have a relatively small effect on the overall resistance of the interconnect when the interconnect is relatively large, but as interconnects become more narrow, these layers use up an increasing amount of the available space within the interconnect and have a far greater effect on the overall interconnect resistivity.
Therefore, it may be advantageous to provide an improved device and process for fabricating a conductive interconnect within a semiconductor device.